1. Field of the Invention
The present invention relates to programmable integrated circuits. More particularly, the present invention relates to non-volatile-memory-based FPGA integrated circuits such as flash-based FPGA integrated circuits and to methods for erasing the non-volatile memory cells that protect the low-voltage devices coupled to the non-volatile memory cells.
2. Background
An non-limiting example of a cell with which the present invention may be used is described in co-pending application Ser. No. 10/319,782 (Act-356) published Jun. 17, 2004 #0114436A1 entitled “PROGRAMMABLE INTERCONNECT CELL FOR CONFIGURING A FIELD PROGRAMMABLE GATE ARRAY.”
One method of erasing this cell is to lower the row line voltage to a level of about −16V, while at least one of the two column lines and one of the two source/drain regions of the non-volatile memory switch are grounded. The row line voltage is limited to about 16V, due to the device breakdown limits of the row-access circuits. The non-volatile memory switch has to be grounded, since most non-volatile memory switches are tied to core logic or the core power or ground, while the core power has to be shut down and grounded during the erase operation.
As shown in FIG. 1, the core power is shut down by a power switch circuit at the chip-internal core supply voltage VCCL, which disconnects the core supply node VCCL at reference numeral 10 from the external Vcc supply voltage to the FPGA core 12 during erase and connects VCCL to ground instead. This is shown implemented by utilizing inverter 14 coupled between VCC and ground. Inverter 14 includes p-channel MOS transistor 16 and n-channel MOS transistor 18 and is driven by the signal CORE OFF 20. During normal circuit operation, the CORE OFF signal 20 is maintained at a low logic level, which causes the output of inverter 12 to assume a high logic level of VCCL. The output of inverter 14 drives the VCCL node 10 to power the core circuits associated with memory cell 22 in FPGA core 12.
For purposes of illustration, an inverter comprised of p-channel transistor 24 and n-channel transistor 26 is shown having its output coupled through non-volatile memory-cell transistor 22 to drive a circuit node (not shown). The bulk of the p-channel transistor 24 is coupled to the VCCL node and the bulks of the n-channel transistor 26 and the non-volatile memory transistor 22 are coupled to ground.
During programming of the non-volatile memory-cell transistor 22 the CORE OFF signal 20 is maintained at a high logic level. This causes the output of inverter 14 to assume a low logic level of ground and removes the VCCL potential from the core circuits (the inverter comprising transistors 24 and 26) associated with memory cell 22.
Persons of ordinary skill in the art will observe that the maximum voltage differential between the column-line and non-volatile memory cell transistor source/drain voltage to the row line voltage at the gate of non-volatile memory cell transistor 22 is limited to 16V. Using this erase potential requires long erase times to achieve the target erase window. Shorter erase times can be achieved by increasing this voltage differential, however, bringing the gate voltage more negative will risk damage or malfunction of the high voltage program/erase transistors (i.e., the row decoders).